1.1’s complement can be easily obtained by using _________
a. Inverter
b. Comparator
c. Adder
d. Subtractor
2.A combinational circuit is one in which the output depends on the
a. present output and the previous output
b. input combination at the time
c. input combination and the previous output
d. input combination at that time and the previous input combination
3.A combinational logic circuit which generates a particular binary word or number is
a. Demultiplexer
b. Decoder
c. Encoder
d. Multiplxer
4.A comparison between serial and parallel adder reveals that serial order
a. operates at the same speed as parallel adder
b. is more complicated
c. is slower
d. is faster
5.A one-to-four line demultiplexer is to be implemented using a memory. How many bits must each word have?
a. 1 bit
b. 2 Bits
c. 4 Bits
d. 8 Bits
6.A positive AND gate is also a negative?
a. XOR Gate
b. NAND Gate
c. OR Gate
d. AND Gate
7.A toggle operation cannot be performed using a single
a. NOR gate
b. AND gate
c. NAND gate
d. OR gate
8.A variable on its own or in its complemented form is known as a __________
a. Sum Term
b. Word
c. Literal
d. Product Term
9.A(A + B) = ?
a. (1 + AB)
b. AB
c. 1
d. A
10.According to boolean law: A + 1 = ?
a. 1
b. A
c. 0
d. A’
11.Adders
a. adds 2 bits
b. All of these
c. is called so because a full adder involves two half-adders
d. needs two input and generates two output
12.An AND circuit
a. is a linear circuit
b. gives an output when all input signals are present simultaneously
c. is a memory circuit
d. is a -ve OR gate
13.An example of a universal building block is:
a. OR Gate
b. EX-NOR gate
c. NOR gate
d. AND gate
14.An OR gate can be imagined as
a. MOS transistors connected in series
b. None of these
c. Switches connected in parallel
d. Switches connected in series
15.DeMorgan’s theorem states that _________
a. (AB)’ = A’ + B’
b. (A + B)’ = A’ * B
c. A’ + B’ = A’B’
d. (AB)’ = A’ + B
16.Don’t care conditions can be used for simplifying Boolean expressions in ___________
a. K-maps
b. Registers
c. Terms
d. Latches
17.Flip flop can hold?
a. 4 bit
b. 1 bit
c. 2 bit
d. 3 bit
18.How many full adders are required to construct an m-bit parallel adder?
a. m
b. m+1
c. m-1
d. m/2
19.How many lines the truth table for a four-input NOR gate would contain to cover all possible input combinations?
a. 16
b. 8
c. 12
d. 4
20.How many truth tables can be made from one function table?
a. ONE
b. Three
c. Any Numbers
d. TWO
21.If a logic gates has four inputs, then total number of possible input combinations is
a. 16
b. 8
c. 9
d. 32
22.If four 4 input multiplexers drive a 4 input multiplexer, we get a:
a. 2 input MUX
b. 16 input MUX
c. 8 input MUX
d. 4 input MUX
23.If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
a. Multiplying
b. Dividing
c. Adding
d. Subtracting
24.In which of the following gates, the output is 1, if and only if at least one input is 1?
a. NOR
b. NAND
c. OR
d. AND
25.Parallel adders are
a. None of these
b. combinational logic circuits
c. sequential logic circuits
d. circuits
26.The characteristic equation of D flip-flop is
a. Q = D’
b. Q = 1
c. Q = D
d. Q = 0
27.The digital multiplexer is basically a combination logic circuit to perform the operation
a. OR-AND
b. AND-or
c. OR-OR
d. AND-and
28.The dual ofthe switching function x + yz is:
a. x̄ + ȳz̄
b. xy(y+z)
c. x̄(ȳ + z̄)
d. X(y+z)
29.The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter?
a. AND
b. NOR
c. NAND
d. XOR
30.The full adder adds the Kth bits of two numbers to the
a. sum of previous bit
b. carry from ( K – 1 )TH bit
c. sum of all previous bits
d. difference of the previous bits
31.The function of a multiplexer is
a. to decode information
b. to transit data on N lines
c. to perform serial to parallel conversion
d. to select 1 out of N input data sources and to transmit it to single channel
32.The inverter OR-gate and AND gate are called decision-making elements because they can recognize some input while disregarding others. A gate recognize a word when its output is
a. bytes,low
b. bytes,high
c. character,low
d. words,high
33.The logical sum of two or more logical product terms is called __________
a. SOP
b. POS
c. OR operation
d. NAND operation
34.The number of two input multiplexers required to construct a 210 input multiplexer is,
a. 1023
b. 10
c. 127
d. 31
35.The output of NOR gate is
a. High if only of its inputs is low
b. High if all of its inputs are low
c. Low if all of its inputs are low
d. High if all of its inputs are high
36.The time required for a gate or inverter to change its state is called?
a. Rise time
b. Charging time
c. Propagation time
d. Decay time
37.There are _____________ Minterms for 3 variables
a. 8
b. 0
c. 2
d. 1
38.Types of circuits:
a. four
b. one
c. three
d. two
39.What is the largest number of data inputs which a data selector with two control inputs can have?
a. 4
b. 3
c. 8
d. 16
40.What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?
a. Two
b. one
c. Four
d. three
41.What logic function is produced by adding an inverter to the output of an AND gate?
a. OR
b. AND
c. NAND
d. NOR
42.Which combination of gates does not allow the implementation of an arbitrary Boolean function?
a. OR gates and NOT gates only
b. NAND gates only
c. OR gates and AND gates only
d. OR gates and exclusive OR gate only
43.Which of the following adders can add three or more numbers at a time?
a. Full adder
b. Carry-save-adder
c. Carry-look-ahead adder
d. Parallel adder
44.Which of the following circuit can be used as parallel to serial converter?
a. Decoder
b. Digital counter
c. Multiplexer
d. Demultiplexer
45.Which of the following circuit can be used as parallel to serial converter?
a. decoder
b. Digital counter
c. multiplexer
d. DEmultiplexer
46.Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate?
a. OR
b. XOR
c. NOT
d. AND
47.Which of the following gates is known as coincidence detector?
a. NOR Gate
b. AND Gate
c. OR Gate
d. NAND Gate
48.Which one of the following set of gates are best suited for ‘parity’ checking and ‘parity’ generation.
a. NOR gates
b. EX-NOR or EX-OR gates
c. AND, OR, NOT gates
d. NAND gates
49.Which one of the following will give the sum of full adders as output ?
a. Three bit parity checker
b. Three bit comparator
c. Three bit Number
d. Three bit counter circuit
50.Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs?
a. Function table
b. Routing table
c. ASCII table
d. Truth table
Answer Key:
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| a | b | b | c | a | c | b | c | a | a |
| 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
| b | b | c | c | a | a | b | c | a | d |
| 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 |
| a | b | a | c | b | c | b | d | d | b |
| 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 |
| d | d | a | a | b | c | a | d | a | d |
| 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 |
| c | c | b | c | c | c | b | b | d | d |
